The present invention relates to a semiconductor device having a function of measuring various types of capacitance such as a line capacitance, a gate capacitance, and a junction capacitance.
In recent years, the ratio of the circuit delay to the line length due to the line capacitance has been increasing along with the increase in the density of a semiconductor device. At the same time, the variations in parameters defining a line have been increasing due to the variations in the manufacturing process conditions, or the like. As a result, the problem of the increasing variations in the circuit delay among semiconductor devices has become more pronounced, and it has become important to monitor variations in the line capacitance.
However, with the line capacitance measurement using a conventional LCR meter, it is necessary to provide a TEG pattern having a large area in order to maintain a desirable measurement precision, and thus it has been difficult to monitor the line capacitance variations in a product chip.
Chen, James C., et al., have developed a CBCM (Charge Based Capacitance Measurement) method as described in Proc. of IEDM 1996 pp. 69-72. With this method, the line capacitance is obtained in terms of current, and thus it is possible to measure the capacitance of a minute line. Therefore, the area of the TEG pattern is reduced. This has made it easy to provide a CBCM measurement circuit pattern in a scribe region, thereby making it possible to monitor the line capacitance variations in each product chip.
Furthermore, it is expected that the CBCM method will make it possible to measure very minute capacitances as follows, which could not be measured in the prior art:
(A) the capacitance of a single contact, the capacitance of a single intersection (cross) between lines, the input/output capacitance of a standard cell;
(B) the capacitance of a single DRAM cell; and
(C) the bit line capacitance connected to a single bit line of a DRAM/SRAM.
The measurement of the capacitance (A) is expected to enable high-precision checking of LPE (Layout Parameter Extraction) results, the measurement of the capacitance (B) is expected to enable optimization of the cell structure and the sense circuit configuration by obtaining statistical distribution data for the cell capacitance, and the measurement of the capacitance (C) is expected to enable optimization of the sense circuit configuration by obtaining matching data for the bit line capacitance.
On the other hand, the evaluation of the gate length of a MIS transistor has been performed by an S & R method (Shift and Ratio method; see Reference 1 (IEEE Electron Device Lett, vol. 13, p. 267, 1992)), or the like, in view of the Id-Vg characteristics of a transistor.
While the S & R method is based on the assumption that the channel resistance is proportional to the channel length, the process of a generation where the design rule is 0.1 μm or less has an increased gate leak due to the reduction in the thickness of the gate oxide film and an increased mobility deterioration due to the increase in the concentration of the substrate in a pocket device, and these phenomena are dependent on the gate length. Therefore, it is becoming less likely that such an assumption holds true, thereby making it difficult to use the S & R method.
Moreover, a method for evaluating the gate length based on the measurement of the gate capacitance is described in Reference 2 (IEEE Electron Device Lett, vol. 5, p. 491, 1984). However, with capacitance measurement using a conventional LCR meter, as with line capacitance measurement, it is necessary to provide a TEG pattern having a large area in order to maintain a desirable measurement precision, whereby it is difficult to use the method for product chips.
As described above, a CBCM pattern is expected to be used for monitoring variations in the gate length because it makes it possible to measure a minute capacitance while reducing the area of the TEG pattern.
FIG. 21 is a block circuit diagram schematically illustrating a circuit configuration of a measurement device for measuring the line capacitance of a semiconductor device using a conventional CBCM method. As illustrated in the figure, the CBCM measurement device includes PMIS transistors MP1 and MP2 and NMIS transistors MN1 and MN2. The PMIS transistor MP1 and the PMIS transistor MP2 have mask dimensions with an equal gate length and an equal gate width, while the NMIS transistor MN1 and the NMIS transistor MN2 have mask dimensions with an equal gate length and an equal gate width.
Moreover, the measurement device further includes a pad NW for supplying a body voltage to the active region of the PMIS transistors MP1 and MP2, a pad Ref for supplying a power supply voltage Vdd to the source of the PMIS transistor MP1, a pad Gp for supplying a control voltage to the respective gates of the PMIS transistors MP1 and MP2, a pad Tst for supplying the power supply voltage Vdd to the source of the PMIS transistor MP2, a pad Gn for supplying a control voltage (control signal) to the respective gates of the NMIS transistors MN1 and MN2, and a pad Gnd for supplying a ground voltage Vss to the respective sources and the active region of the NMIS transistors MN1 and MN2.
The CBCM measurement device has a reference capacitance Cref between a node N1 (which is connected to the respective drains of the PMIS transistor MP1 and the NMIS transistor MN1) and the pad Gnd, and a test capacitance Ctst between a node N2 (which is connected to the respective drains of the PMIS transistor MP2 and the NMIS transistor MN2) and the pad Gnd. The reference capacitance Cref is equal to a dummy capacitance Cm, which is the capacitance of the drain contact, the line on the contact, etc., of each transistor. Note however that the dummy capacitance Cm does not include a drain junction capacitance Cj or a gate-drain capacitance Cgd of the transistor. The test capacitance Ctst is equal to the sum of the dummy capacitance Cm and a target capacitance Ct(=Cm+Ct).
Herein, the purpose of the measurement device is to measure the target capacitance Ct, which may be, for example, the capacitance of a line to be measured, the capacitance between the gate and the substrate, or the capacitance of a plug.
FIG. 22 is a timing chart illustrating the temporal transitions of the gate control signals supplied from the pads Gp and Gn to the respective transistors and the potential at the nodes N1 and N2 in the measurement device illustrated in FIG. 21.
Herein, the potential is fixed to the power supply voltage Vdd at the pads Ref, Tst and Nw, and the potential at the pad Gnd is fixed to the ground voltage Vss. As illustrated in the figure, the gate control signals supplied from the pads Gp and Gn to the gates of the transistors MP1, MP2, MN1 and MN2 transition so that one of the PMIS transistor MP1 and the NMIS transistor MN1 and one of the PMIS transistor MP2 and the NMIS transistor MN2 are ON at any time. Thus, the through current flowing from the PMIS transistor MP1 to the NMIS transistor MN1 and the through current flowing from the PMIS transistor MP2 to the NMIS transistor MN2 do not occur at the same timing.
As illustrated in FIG. 22, during the period between t1 and t2, the PMIS transistors MP1 and MP2 are both ON. Therefore, through currents I1 and I2 flow to charge the capacitors Cref and Ctst. During the same period, the NMIS transistors MN1 and MN2 are both OFF. Therefore, the respective potentials at the nodes N1 and N2, which are connected to the capacitors Cref and Ctst, respectively, both reach the power supply voltage Vdd.
On the other hand, during the period between t2 and t3, all of the transistors MP1, MP2, MN1 and MN2 are OFF. Ideally, it can be regarded that the charges stored in the capacitors Cref and Ctst are preserved. Therefore, the nodes N1 and N2 remain to be at the potential of the power supply voltage Vdd.
During the period between t3 and t4, only the NMIS transistors MN1 and MN2 are ON. Therefore, the capacitors Cref and Ctst are discharged, and the potentials at the nodes N1 and N2 reach the ground voltage Vss. On the other hand, during the period between t4 and t5, all of the transistors are OFF. Ideally, the capacitors Cref and Ctst remain to be at the potential Vss, i.e., the potential upon completion of the discharge process. The operation as described above is performed in one cycle, and the operation is repeated. The measurement device measures the time average value for the currents I1 and I2.
Herein, assuming that the frequency of the gate control signal supplied from each of the pads Gp and Gn is f(=1/T; T is the period of time from t1 to t5), Expression (1) below holds:                                                                         I2                -                I1                            =                                                (                                      Ctst                    ·                                          Vdd                      /                      T                                                        )                                -                                  (                                      Cref                    ·                                          Vdd                      /                      T                                                        )                                                                                                        =                                                (                                      Cm                    +                    Ct                    +                    Ctr                    -                    Cm                    -                    Ctr                                    )                                ·                                  Vdd                  /                  T                                                                                                        =                              (                                  Ct                  ·                  Vdd                  ·                  f                                )                                                                        (        1        )            In Expression (1) above, Ctr is the capacitance connected to the drain terminal of a transistor, and the capacitance Ctr is equal to the sum of the drain junction capacitance Cj and the gate-drain overlap capacitance Cgd.
Based on Expression (1) above, the target capacitance Ct can be given by Expression (2) below:Ct=(I2−I1)/(Vdd·f)  (2)One advantage of the CBCM method is that it is possible to obtain the intended target capacitance Ct by canceling out the dummy capacitance and the parasitic capacitance of the transistor as shown in Expression (1). Note however that this method has error factors as follows.Error Factors of CBCM Method
As disclosed in Reference 2 (Proc. of IEDM 1996 pp. 69-72), the error factors of the CBCM method include: 1) an error due to the poor precision of the measurement device; and 2) a mismatch between a pair of transistors, and these errors occur due to the following causes.
1) Specifically, the precision of the measurement device includes the precisions of the voltage source and the ammeter connected to the pads Ref and Tst, and the precision of the frequency of the pulse generator connected to the pads Gp and Gn.
2) Specifically, the mismatch between a pair of transistors means that although the PMIS transistors MP1 and MP2, and the NMIS transistors MN1 and MN2, are equally-sized in terms of the mask, they may differ from each other in terms of the junction capacitance, the gate-drain overlap capacitance, etc., due to the variations in the process conditions.
Moreover, as shown in Expression (1) above, the mismatch in the parasitic capacitance between a pair of transistors is one factor that determines the measurement precision. Note that in Reference 2, the error 2) is estimated to be 30 aF or less.
Moreover, beside the error 2), another process-related error is 3) the leak component of a transistor during an OFF period.
3) Specifically, the transistor leak components during an OFF period includes the OFF leak current of the NMIS transistors, the OFF leak current of the PMIS transistors, the tunneling current between the gate and the substrate, and the junction leak current, which may occur during the period between t4 and t5, during which all of the transistors illustrated in FIG. 22 are OFF. When these leak components are large, the potentials at the nodes N1 and N2 are floating up from the ideal potential Vss that is reached upon completion of a discharge process, whereby the nodes N1 and N2 are charged with a potential difference that is smaller than Vdd−Vss, thereby reducing the evaluated capacitance value.
However, when the CBCM method is used for
(1) measuring a very minute capacitance;
(2) monitoring the line capacitance variations;
(3) measuring the input/output capacitance of a standard cell or the DRAM/SRAM bit line capacitance; and
(4) monitoring the gate length variations, the following problems arise.
(1) Problem with Very Minute Capacitance Measurement
During the period between t4 and t5 as illustrated in FIG. 22 (“period A”), all of the transistors are OFF, and the nodes N1 and N2 ideally remain to be at the ground potential Vss. However, strictly speaking, the potentials at the nodes N1 and N2 fluctuate.
FIG. 23 is a more detailed version of the timing chart of FIG. 22. As illustrated in FIG. 23, during the period between t41 and t4, all of the transistors are OFF, and the potential at the pad Gn for turning the NMIS transistors MN1 and MN2 ON/OFF is falling, whereby the potentials at the nodes N1 and N2 are floating down from the ground potential Vss by δVss due to an undershoot. As a result, the nodes N1 and N2 are charged with a potential difference that is larger than Vdd−Vss, whereby the evaluated capacitance value is greater than the actual capacitance value. Moreover, during the period between t21 and t2, all of the transistors are OFF, and the potential at the pad Gp for turning the PMIS transistors MP1 and MP2 ON/OFF is rising, whereby the potentials at the nodes N1 and N2 are floating up from Vdd by δVdd due to an overshoot. As a result, the nodes N1 and N2 are charged with a potential difference that is larger than Vdd−Vss, whereby the evaluated capacitance value is greater than the actual capacitance value.
Moreover, during the period between t21 and t2, the potential at the pad Gp for turning the PMIS transistors MP1 and MP2 ON/OFF is rising, whereby a current flows into the PMIS transistors MP1 and MP2 via a gate-drain overlap capacitor. This also lowers the precision of the evaluated capacitance value.
Each of FIG. 24A to FIG. 24D shows a portion of the timing chart of FIG. 23 in an enlarged manner to illustrate a change in the voltage due to an overshoot. FIG. 24A and FIG. 24B illustrate the voltage at the node Ni (broken line) and the voltage at the node N2 (solid line), respectively, during the period between t40 and t5 illustrated in FIG. 23. FIG. 24C and FIG. 24D illustrate the voltage at the node N1 (broken line) and the voltage at the node N2 (solid line), respectively, during the period between t20 and t3 illustrated in FIG. 23.
As illustrated in FIG. 24A and FIG. 24B, the voltage decrease δVss from the ground potential is larger as the value of the dummy capacitance Cm is smaller. This is because an undershoot is due to the gate-drain overlap capacitor, which is a mirror capacitor, whereby the voltage decrease δVss is proportional to Cgd/(Cm+Ct+Cj+Cgd).
Moreover, as illustrated in FIG. 24C and FIG. 24D, the value of δVdd is larger as the value of the dummy capacitance Cm is smaller. This is because the voltage increase δVdd due to an overshoot is proportional to Cgd/(Cm+Ct+Cj+Cgd).
Since the absolute value of the current flowing in a PMIS transistor is proportional to δVdd, the absolute value of the current value I1 of the reference transistor is larger than the absolute value of the current value I2 of the target transistor.
Moreover, in a discharge operation, the sign of the current is opposite to that in a charge operation, whereby the relationship I2>I1 holds as in a charge operation. This means an apparent increase in the evaluated capacitance value.
With the problem (1) as described above, the evaluated capacitance value apparently increases if there is a large voltage increase/decrease due to an overshoot/undershoot of the potentials at the nodes N1 and N2 caused by the gate-drain overlap capacitance.
(2) Problem with Monitoring of Line Capacitance Variations
FIG. 25A and FIG. 25B are plan views illustrating different types of line patterns to be evaluated. FIG. 26A and FIG. 26B illustrate different types of line capacitance components between lines in the same wiring layer. FIG. 27 illustrates different types of line capacitance components, taking into consideration not only the capacitance between two lines in the same wiring layer but also the capacitance with a line in a different wiring layer or with the substrate.
As illustrated in FIG. 25A and FIG. 25B, line patterns to be evaluated are generally classified into two types, i.e., a single line pattern as illustrated in FIG. 25A and a periodic L/S pattern (line and space pattern) as illustrated in FIG. 25B. As illustrated in FIG. 26A, in a single line pattern, all the lines other than the subject line to be evaluated are grounded, whereby the capacitance of the subject line is obtained by summing up the capacitance C12 between the subject line and an adjacent line together with capacitances C13, C14, C15, . . . , between the subject line and other lines. Moreover, as illustrated in FIG. 25B, a periodic L/S pattern includes two comb-shaped patterns meshed with each other. With a periodic L/S pattern, every other line is given a potential, and there is a potential distribution symmetry at opposing edges of the boundary shown in FIG. 26B. Therefore, a periodic L/S pattern is advantageous in that the analysis in a capacitance simulation is easy.
When measuring a line capacitance in an actual semiconductor integrated circuit device, the structure of the bus line or the bit line is closer to that shown in FIG. 25B, but the pattern illustrated in FIG. 25A generally accounts for the majority of cases. The patterns illustrated in FIG. 25A and FIG. 25B both aim at obtaining a capacitance per unit length while taking into consideration only the two-dimensional cross-sectional area.
However, it is difficult to use the CBCM method for measuring the capacitance of a pattern illustrated in FIG. 25A or FIG. 25B for the following reason. Since a CBCM pattern is based on the assumption that it is to be provided in a scribe region, the pattern has a reduced area. As a result, the pattern is significantly shifted from the shape with which it is only necessary to take into consideration the ideal two-dimensional cross-sectional area of the line, and this shift causes an error in the measured line capacitance value.
For example, an error is caused by a fringe capacitance component due to the three-dimensional shape of capacitors Cfy1 or Cfy2 illustrated in FIG. 25A or capacitors Cfx, Cfy, Cfxy1 or Cfxy2 illustrated in FIG. 25B.
Furthermore, the line capacitance component includes, in addition to the line capacitance C1 between lines in the same wiring layer, a capacitance Cv between the subject line and a line in another wiring layer, as illustrated in FIG. 27. However, it is not easy in the prior art to separate such a line capacitance component in a certain line pattern.
(3) Problem with Measurement of Input/Output Capacitance of Standard Cell, or the Like.
The input/output capacitance of a standard cell or the bit line capacitance of a DRAM/SRAM both include capacitance components with voltage dependence such as the gate capacitance and the junction capacitance, in addition to the line capacitance. Therefore, whether or not such a capacitance can be evaluated with a high precision is dependent on whether or not it is possible to evaluate the C-V characteristics (the voltage dependence of a capacitance).
FIG. 28 is a graph illustrating the gate voltage Vgb dependence of a gate capacitance Cgg, which is obtained by an HSPICE simulation and the CBCM method. Typically, in a transistor, the voltage Vgb applied between the gate and the substrate changes with the source, the drain and the substrate being shorted together. In the figure, the symbol “⋄” (BSIM3) denotes data of a standard model included in the HSPICE simulation. On the other hand, the measurement by the CBCM method was performed as follows. The gate control signals from the pads Gp and Gn illustrated in FIG. 22 were input to a CBCM measurement device pattern, which is illustrated in FIG. 10A and will be described later, and the capacitance value was calculated based on Expression (2) by integrating the currents 11 and 12 flowing through the nodes N1 and N2, respectively.
The CBCM circuit simulation is performed by using a BSIM3 model. Therefore, the results of the CBCM circuit simulation should ideally coincide with those of the BSIM3 simulation. However, as can be seen from FIG. 28, the results are quite different from each other. Moreover, in the CBCM measurement, it is necessary to apply a power supply voltage Vdd that is equal to or greater than the threshold voltage of the transistor. Therefore, data is not obtained at all in a region where the gate voltage Vgb is low (0.5 or less in the figure). Also in a region where the gate voltage Vgb is high (0.7 or more in the figure), the capacitance value estimated by using the CBCM method is smaller than the ideal BSIM3 capacitance value.
(4) Problem with Monitoring of Gate Length Variations
The process of a generation where the design rule is 0.1 μm or less has an increased gate leak due to the reduction in the thickness of the gate oxide film. With the measurement by a conventional LCR method, the conductance component of the gate leak is as large as the capacitance component ωC (=2πfC), thereby resulting in a large capacitance measurement error.
In the CBCM method, the proportion of the gate leak with respect to the measured current can be relatively reduced by increasing the measurement frequency f. However, when externally applying a gate control signal as illustrated in FIG. 22, there is an upper limit for the measurement frequency f. Moreover, while the measurement device itself is capable of operating with a frequency ranging from a frequency on the order of 10 MHz to a frequency of 100 MHz, the resonance frequency is on the order of MHz in the measurement system (particularly the coaxial signal line). Therefore, taking some margin into consideration, the upper limit for the measurement frequency is about 1 MHz. Thus, it is difficult to remove the influence of the gate leak from the measured capacitance value.